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<a href="#nested-classes">Data Structures</a> &#124;
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<a name="details" id="details"></a><h2 class="groupheader">Overview</h2>
<div class="textblock"><p>This header file contains the identifiers and basic driver functions (or macros) that can be used to access the device. </p>
<p>Other driver functions are defined in <a class="el" href="xavb_8h.html" title="This header file contains the identifiers and basic driver functions (or macros) that can be used to ...">xavb.h</a>.</p>
<pre>
MODIFICATION HISTORY:</pre><pre>Ver   Who  Date     Changes
</p>
<hr/>
<p>
1.00a mbr  09/19/08 First release
1.01a mbr  06/24/09 PTP frame format updates for IEEE802.1 AS draft 5-0
2_02a mbr  09/16/09 Updates for programmable PTP timers
2_04a kag  07/23/10 PTP frame format updates for IEEE802.1 AS draft 6-7
3_01a kag  08/29/11 Added new APIs to update the RX Filter Control Reg.
              Fix for CR:572539. Updated bit map for Rx Filter
              control reg.
3_01a asa  04/10/12 The AVB core is now brought inside the AxiEthernet
              core. Because of this there are changes in the
              register map.</pre><pre></pre> </div><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="nested-classes"></a>
Data Structures</h2></td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_avb___rtc_format.html">XAvb_RtcFormat</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">This typedef defines the format for the Real Time Clock (RTC).  <a href="struct_x_avb___rtc_format.html#details">More...</a><br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_avb___uint64.html">XAvb_Uint64</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">This typedef describes a 64-bit un-signed integer in terms of 2 u32s.  <a href="struct_x_avb___uint64.html#details">More...</a><br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:a74fc84434da6ed0d4604020e9bed3a8b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xavb__hw_8h.html#a74fc84434da6ed0d4604020e9bed3a8b">XAvb_ReadReg</a>(BaseAddress, RegOffset)&#160;&#160;&#160;Xil_In32((BaseAddress) + (RegOffset))</td></tr>
<tr class="memdesc:a74fc84434da6ed0d4604020e9bed3a8b"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro reads from the given AVB core register.  <a href="#a74fc84434da6ed0d4604020e9bed3a8b">More...</a><br/></td></tr>
<tr class="separator:a74fc84434da6ed0d4604020e9bed3a8b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a74f3dcc0fed12b1ee97541a109b8d98c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xavb__hw_8h.html#a74f3dcc0fed12b1ee97541a109b8d98c">XAvb_WriteReg</a>(BaseAddress, RegOffset, Data)&#160;&#160;&#160;Xil_Out32((BaseAddress) + (RegOffset), (Data))</td></tr>
<tr class="memdesc:a74f3dcc0fed12b1ee97541a109b8d98c"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro writes to the given AVB core register.  <a href="#a74f3dcc0fed12b1ee97541a109b8d98c">More...</a><br/></td></tr>
<tr class="separator:a74f3dcc0fed12b1ee97541a109b8d98c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a072d5c22a5ff3e25e036146d552955bc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xavb__hw_8h.html#a072d5c22a5ff3e25e036146d552955bc">XAvb_ReadPtpBuffer</a>(BaseAddress, PtpPacketBaseAddress, PtpPacketOffset)&#160;&#160;&#160;Xil_In32(BaseAddress + PtpPacketBaseAddress + PtpPacketOffset)</td></tr>
<tr class="memdesc:a072d5c22a5ff3e25e036146d552955bc"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro reads from the given PTP frame buffer.  <a href="#a072d5c22a5ff3e25e036146d552955bc">More...</a><br/></td></tr>
<tr class="separator:a072d5c22a5ff3e25e036146d552955bc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aeab8d086419859c0676c181c38252640"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xavb__hw_8h.html#aeab8d086419859c0676c181c38252640">XAvb_WritePtpBuffer</a>(BaseAddress, PtpPacketBaseAddress, PtpPacketOffset, Data)&#160;&#160;&#160;Xil_Out32(BaseAddress + PtpPacketBaseAddress + PtpPacketOffset, (Data))</td></tr>
<tr class="memdesc:aeab8d086419859c0676c181c38252640"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro writes to the given PTP frame buffer.  <a href="#aeab8d086419859c0676c181c38252640">More...</a><br/></td></tr>
<tr class="separator:aeab8d086419859c0676c181c38252640"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac935987ce15937b9a2b77a104f559bde"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xavb__hw_8h.html#ac935987ce15937b9a2b77a104f559bde">XAvbMac_ReadConfig</a>(BaseAddress, RegOffset)&#160;&#160;&#160;Xil_In32((BaseAddress) + (RegOffset))</td></tr>
<tr class="memdesc:ac935987ce15937b9a2b77a104f559bde"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro reads from the given TEMAC Configuration Register.  <a href="#ac935987ce15937b9a2b77a104f559bde">More...</a><br/></td></tr>
<tr class="separator:ac935987ce15937b9a2b77a104f559bde"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad6392e55a276101131666b02007ed4c3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xavb__hw_8h.html#ad6392e55a276101131666b02007ed4c3">XAvbMac_WriteConfig</a>(BaseAddress, RegOffset, Data)&#160;&#160;&#160;Xil_Out32((BaseAddress) + (RegOffset), (Data))</td></tr>
<tr class="memdesc:ad6392e55a276101131666b02007ed4c3"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro writes to the given TEMAC Configuration Register.  <a href="#ad6392e55a276101131666b02007ed4c3">More...</a><br/></td></tr>
<tr class="separator:ad6392e55a276101131666b02007ed4c3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae599ca8c254011bb4ee0191e32327ee9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xavb__hw_8h.html#ae599ca8c254011bb4ee0191e32327ee9">XAvbMac_ReadMdio</a>(BaseAddress, Phyad, Regad)</td></tr>
<tr class="memdesc:ae599ca8c254011bb4ee0191e32327ee9"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro reads from the given MDIO Register using the TEMAC.  <a href="#ae599ca8c254011bb4ee0191e32327ee9">More...</a><br/></td></tr>
<tr class="separator:ae599ca8c254011bb4ee0191e32327ee9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a92871886d069080e57c72754659f4846"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xavb__hw_8h.html#a92871886d069080e57c72754659f4846">XAvbMac_WriteMdio</a>(BaseAddress, Phyad, Regad, Data)</td></tr>
<tr class="memdesc:a92871886d069080e57c72754659f4846"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro writes to the given MDIO Register using the TEMAC.  <a href="#a92871886d069080e57c72754659f4846">More...</a><br/></td></tr>
<tr class="separator:a92871886d069080e57c72754659f4846"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Register offsets for the Tri-Mode Ethernet MAC. Each register is 32</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>bits.</p>
<p>The MAC is addressable through the Ethernet AVB Endpoint core. </p>
</div></td></tr>
<tr class="memitem:a3ba68470fe0e86604ad06c3e909aa7a9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xavb__hw_8h.html#a3ba68470fe0e86604ad06c3e909aa7a9">XAVB_MAC_RX_REG0_OFFSET</a>&#160;&#160;&#160;0x00000400</td></tr>
<tr class="memdesc:a3ba68470fe0e86604ad06c3e909aa7a9"><td class="mdescLeft">&#160;</td><td class="mdescRight">MAC Rx Config Register 0.  <a href="#a3ba68470fe0e86604ad06c3e909aa7a9">More...</a><br/></td></tr>
<tr class="separator:a3ba68470fe0e86604ad06c3e909aa7a9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac563b910c3a0bb2b55d2b3b1d8465101"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xavb__hw_8h.html#ac563b910c3a0bb2b55d2b3b1d8465101">XAVB_MAC_RX_REG1_OFFSET</a>&#160;&#160;&#160;0x00000404</td></tr>
<tr class="memdesc:ac563b910c3a0bb2b55d2b3b1d8465101"><td class="mdescLeft">&#160;</td><td class="mdescRight">MAC Rx Config Register 1.  <a href="#ac563b910c3a0bb2b55d2b3b1d8465101">More...</a><br/></td></tr>
<tr class="separator:ac563b910c3a0bb2b55d2b3b1d8465101"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af573ab840d4c0f06dbecb120f4a8950f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xavb__hw_8h.html#af573ab840d4c0f06dbecb120f4a8950f">XAVB_MAC_TX_REG_OFFSET</a>&#160;&#160;&#160;0x00000408</td></tr>
<tr class="memdesc:af573ab840d4c0f06dbecb120f4a8950f"><td class="mdescLeft">&#160;</td><td class="mdescRight">MAC Tx Config Register.  <a href="#af573ab840d4c0f06dbecb120f4a8950f">More...</a><br/></td></tr>
<tr class="separator:af573ab840d4c0f06dbecb120f4a8950f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae5d89c2164737985208dda027b8d0387"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xavb__hw_8h.html#ae5d89c2164737985208dda027b8d0387">XAVB_MAC_FC_REG_OFFSET</a>&#160;&#160;&#160;0x0000040c</td></tr>
<tr class="memdesc:ae5d89c2164737985208dda027b8d0387"><td class="mdescLeft">&#160;</td><td class="mdescRight">MAC Flow Control Register.  <a href="#ae5d89c2164737985208dda027b8d0387">More...</a><br/></td></tr>
<tr class="separator:ae5d89c2164737985208dda027b8d0387"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a31ebb43f9bfd2a258493dc13f01a7f0b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xavb__hw_8h.html#a31ebb43f9bfd2a258493dc13f01a7f0b">XAVB_MAC_SPD_REG_OFFSET</a>&#160;&#160;&#160;0x00000410</td></tr>
<tr class="memdesc:a31ebb43f9bfd2a258493dc13f01a7f0b"><td class="mdescLeft">&#160;</td><td class="mdescRight">MAC Speed Control Register.  <a href="#a31ebb43f9bfd2a258493dc13f01a7f0b">More...</a><br/></td></tr>
<tr class="separator:a31ebb43f9bfd2a258493dc13f01a7f0b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Register offsets for the Ethernet Audio Video Endpoint. Each register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>is 32 bits. </p>
</div></td></tr>
<tr class="memitem:ad99ca00362bea7facdddcc2cf4b665da"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xavb__hw_8h.html#ad99ca00362bea7facdddcc2cf4b665da">XAVB_PTP_TX_CONTROL_OFFSET</a>&#160;&#160;&#160;0x00012000</td></tr>
<tr class="memdesc:ad99ca00362bea7facdddcc2cf4b665da"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tx PTP Control Reg.  <a href="#ad99ca00362bea7facdddcc2cf4b665da">More...</a><br/></td></tr>
<tr class="separator:ad99ca00362bea7facdddcc2cf4b665da"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad0d33dc36a4a6b1f046d7ad862775922"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xavb__hw_8h.html#ad0d33dc36a4a6b1f046d7ad862775922">XAVB_PTP_RX_CONTROL_OFFSET</a>&#160;&#160;&#160;0x00012004</td></tr>
<tr class="memdesc:ad0d33dc36a4a6b1f046d7ad862775922"><td class="mdescLeft">&#160;</td><td class="mdescRight">Rx PTP Control Reg.  <a href="#ad0d33dc36a4a6b1f046d7ad862775922">More...</a><br/></td></tr>
<tr class="separator:ad0d33dc36a4a6b1f046d7ad862775922"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aeb18774c7074b8558f6f3d92ee894308"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xavb__hw_8h.html#aeb18774c7074b8558f6f3d92ee894308">XAVB_RX_FILTER_CONTROL</a>&#160;&#160;&#160;0x00012008</td></tr>
<tr class="memdesc:aeb18774c7074b8558f6f3d92ee894308"><td class="mdescLeft">&#160;</td><td class="mdescRight">Rx Filter Control Reg.  <a href="#aeb18774c7074b8558f6f3d92ee894308">More...</a><br/></td></tr>
<tr class="separator:aeb18774c7074b8558f6f3d92ee894308"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a634b68c6d85a3fbadd2b6feb56a62d62"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xavb__hw_8h.html#a634b68c6d85a3fbadd2b6feb56a62d62">XAVB_TX_SENDSLOPE</a>&#160;&#160;&#160;0x0001200C</td></tr>
<tr class="memdesc:a634b68c6d85a3fbadd2b6feb56a62d62"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tx rate sendSlope Reg.  <a href="#a634b68c6d85a3fbadd2b6feb56a62d62">More...</a><br/></td></tr>
<tr class="separator:a634b68c6d85a3fbadd2b6feb56a62d62"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a355862c65f81390538cf5e8b19493ea5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xavb__hw_8h.html#a355862c65f81390538cf5e8b19493ea5">XAVB_TX_IDLESLOPE</a>&#160;&#160;&#160;0x00012010</td></tr>
<tr class="memdesc:a355862c65f81390538cf5e8b19493ea5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tx rate idleSlope Reg.  <a href="#a355862c65f81390538cf5e8b19493ea5">More...</a><br/></td></tr>
<tr class="separator:a355862c65f81390538cf5e8b19493ea5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa8ecc322bb424bdd59e02a09b7a91279"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xavb__hw_8h.html#aa8ecc322bb424bdd59e02a09b7a91279">XAVB_TX_HILIMIT</a>&#160;&#160;&#160;0x00012014</td></tr>
<tr class="memdesc:aa8ecc322bb424bdd59e02a09b7a91279"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tx rate hiLimit Reg.  <a href="#aa8ecc322bb424bdd59e02a09b7a91279">More...</a><br/></td></tr>
<tr class="separator:aa8ecc322bb424bdd59e02a09b7a91279"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a77bc297f703b667990fe302c8d7765ac"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xavb__hw_8h.html#a77bc297f703b667990fe302c8d7765ac">XAVB_TX_LOLIMIT</a>&#160;&#160;&#160;0x00012018</td></tr>
<tr class="memdesc:a77bc297f703b667990fe302c8d7765ac"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tx rate loLimit Reg.  <a href="#a77bc297f703b667990fe302c8d7765ac">More...</a><br/></td></tr>
<tr class="separator:a77bc297f703b667990fe302c8d7765ac"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a17b4489a857a0fcb761a529b749d5ad3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xavb__hw_8h.html#a17b4489a857a0fcb761a529b749d5ad3">XAVB_RTC_NANOSEC_OFFSET</a>&#160;&#160;&#160;0x00012800</td></tr>
<tr class="memdesc:a17b4489a857a0fcb761a529b749d5ad3"><td class="mdescLeft">&#160;</td><td class="mdescRight">RTC ns offset Reg.  <a href="#a17b4489a857a0fcb761a529b749d5ad3">More...</a><br/></td></tr>
<tr class="separator:a17b4489a857a0fcb761a529b749d5ad3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acc7285ad5177c30185fcd6e39992865b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xavb__hw_8h.html#acc7285ad5177c30185fcd6e39992865b">XAVB_RTC_SEC_LOWER_OFFSET</a>&#160;&#160;&#160;0x00012808</td></tr>
<tr class="memdesc:acc7285ad5177c30185fcd6e39992865b"><td class="mdescLeft">&#160;</td><td class="mdescRight">RTC sec[31:0] offset.  <a href="#acc7285ad5177c30185fcd6e39992865b">More...</a><br/></td></tr>
<tr class="separator:acc7285ad5177c30185fcd6e39992865b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac8683f10accad0c3fbb9ed86f7e63577"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xavb__hw_8h.html#ac8683f10accad0c3fbb9ed86f7e63577">XAVB_RTC_SEC_UPPER_OFFSET</a>&#160;&#160;&#160;0x0001280C</td></tr>
<tr class="memdesc:ac8683f10accad0c3fbb9ed86f7e63577"><td class="mdescLeft">&#160;</td><td class="mdescRight">RTC sec[47:32] offset.  <a href="#ac8683f10accad0c3fbb9ed86f7e63577">More...</a><br/></td></tr>
<tr class="separator:ac8683f10accad0c3fbb9ed86f7e63577"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a48d76d16f8d685a65a1216614e548071"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xavb__hw_8h.html#a48d76d16f8d685a65a1216614e548071">XAVB_RTC_INCREMENT_OFFSET</a>&#160;&#160;&#160;0x00012810</td></tr>
<tr class="memdesc:a48d76d16f8d685a65a1216614e548071"><td class="mdescLeft">&#160;</td><td class="mdescRight">RTC Increment Reg.  <a href="#a48d76d16f8d685a65a1216614e548071">More...</a><br/></td></tr>
<tr class="separator:a48d76d16f8d685a65a1216614e548071"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a59f550eaa57148613974c4aa5628bfb4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xavb__hw_8h.html#a59f550eaa57148613974c4aa5628bfb4">XAVB_RTC_NANOSEC_VALUE_OFFSET</a>&#160;&#160;&#160;0x00012814</td></tr>
<tr class="memdesc:a59f550eaa57148613974c4aa5628bfb4"><td class="mdescLeft">&#160;</td><td class="mdescRight">RTC ns value Reg.  <a href="#a59f550eaa57148613974c4aa5628bfb4">More...</a><br/></td></tr>
<tr class="separator:a59f550eaa57148613974c4aa5628bfb4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa71292011b875c192d09141638c3a4e1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xavb__hw_8h.html#aa71292011b875c192d09141638c3a4e1">XAVB_RTC_SEC_LOWER_VALUE_OFFSET</a>&#160;&#160;&#160;0x00012818</td></tr>
<tr class="memdesc:aa71292011b875c192d09141638c3a4e1"><td class="mdescLeft">&#160;</td><td class="mdescRight">RTC sec[31:0] value.  <a href="#aa71292011b875c192d09141638c3a4e1">More...</a><br/></td></tr>
<tr class="separator:aa71292011b875c192d09141638c3a4e1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae38e8307c8da64ba9f42516168855a8f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xavb__hw_8h.html#ae38e8307c8da64ba9f42516168855a8f">XAVB_RTC_SEC_UPPER_VALUE_OFFSET</a>&#160;&#160;&#160;0x0001281C</td></tr>
<tr class="memdesc:ae38e8307c8da64ba9f42516168855a8f"><td class="mdescLeft">&#160;</td><td class="mdescRight">RTC sec[47:32] value.  <a href="#ae38e8307c8da64ba9f42516168855a8f">More...</a><br/></td></tr>
<tr class="separator:ae38e8307c8da64ba9f42516168855a8f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2f724f6845f2fc8b62dc841ef36525d5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xavb__hw_8h.html#a2f724f6845f2fc8b62dc841ef36525d5">XAVB_RTC_CLEAR_INT_OFFSET</a>&#160;&#160;&#160;0x00012820</td></tr>
<tr class="memdesc:a2f724f6845f2fc8b62dc841ef36525d5"><td class="mdescLeft">&#160;</td><td class="mdescRight">RTC Interrupt Clear.  <a href="#a2f724f6845f2fc8b62dc841ef36525d5">More...</a><br/></td></tr>
<tr class="separator:a2f724f6845f2fc8b62dc841ef36525d5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af86466362cc51296ae22fd1cb6c1d6ad"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xavb__hw_8h.html#af86466362cc51296ae22fd1cb6c1d6ad">XAVB_RTC_8K_OFFSET_OFFSET</a>&#160;&#160;&#160;0x00012824</td></tr>
<tr class="memdesc:af86466362cc51296ae22fd1cb6c1d6ad"><td class="mdescLeft">&#160;</td><td class="mdescRight">RTC 8k phase offset.  <a href="#af86466362cc51296ae22fd1cb6c1d6ad">More...</a><br/></td></tr>
<tr class="separator:af86466362cc51296ae22fd1cb6c1d6ad"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae9e3a0562e191d4ea8eb166f5deadef3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xavb__hw_8h.html#ae9e3a0562e191d4ea8eb166f5deadef3">XAVB_SW_RESET_OFFSET</a>&#160;&#160;&#160;0x00012828</td></tr>
<tr class="memdesc:ae9e3a0562e191d4ea8eb166f5deadef3"><td class="mdescLeft">&#160;</td><td class="mdescRight">S/W Reset Reg.  <a href="#ae9e3a0562e191d4ea8eb166f5deadef3">More...</a><br/></td></tr>
<tr class="separator:ae9e3a0562e191d4ea8eb166f5deadef3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Packet base address offsets for the Ethernet Audio Video Endpoint Tx</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Precise Timing Protocol (PTP) frame buffer.</p>
<p>Each PTP frames is stored in 256-byte chunks of BRAM. This BRAM can store 8 PTP frames of which only 6 are currently in use. </p>
</div></td></tr>
<tr class="memitem:a6b7c29da7c7f49a541bae584bf94c559"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a6b7c29da7c7f49a541bae584bf94c559"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_PTP_TX_SYNC_OFFSET</b>&#160;&#160;&#160;0x00011000</td></tr>
<tr class="separator:a6b7c29da7c7f49a541bae584bf94c559"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2461b11951e9884926d2f41aa6fbc7cf"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a2461b11951e9884926d2f41aa6fbc7cf"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_PTP_TX_FOLLOW_UP_OFFSET</b>&#160;&#160;&#160;0x00011100</td></tr>
<tr class="separator:a2461b11951e9884926d2f41aa6fbc7cf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a25e98373619aec43e26b143f7dd772b8"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a25e98373619aec43e26b143f7dd772b8"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_PTP_TX_PDELAYREQ_OFFSET</b>&#160;&#160;&#160;0x00011200</td></tr>
<tr class="separator:a25e98373619aec43e26b143f7dd772b8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae6c73d16c51dfb887ee8e6e59158a156"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ae6c73d16c51dfb887ee8e6e59158a156"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_PTP_TX_PDELAYRESP_OFFSET</b>&#160;&#160;&#160;0x00011300</td></tr>
<tr class="separator:ae6c73d16c51dfb887ee8e6e59158a156"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a884b7b765c3222fb63680269ca1bd4b5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a884b7b765c3222fb63680269ca1bd4b5"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_PTP_TX_PDELAYRESP_FOLLOW_UP_OFFSET</b>&#160;&#160;&#160;0x00011400</td></tr>
<tr class="separator:a884b7b765c3222fb63680269ca1bd4b5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0c20629ddd1fe54531e00a9bb097619f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a0c20629ddd1fe54531e00a9bb097619f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_PTP_TX_ANNOUNCE_OFFSET</b>&#160;&#160;&#160;0x00011500</td></tr>
<tr class="separator:a0c20629ddd1fe54531e00a9bb097619f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Base address offset for the Ethernet Audio Video Endpoint Rx</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Precise Timing Protocol (PTP) frame buffer.</p>
<p>These PTP frames are stored in 256-byte chunks of BRAM. This BRAM can store 16 PTP frames. </p>
</div></td></tr>
<tr class="memitem:a9106ea16ef7e55defa178b3af9fa12b4"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a9106ea16ef7e55defa178b3af9fa12b4"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_PTP_RX_BASE_OFFSET</b>&#160;&#160;&#160;0x00010000</td></tr>
<tr class="separator:a9106ea16ef7e55defa178b3af9fa12b4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">AVB Tx PTP Control Register</div></td></tr>
<tr class="memitem:a23d0575e79fffc06dba35ebf43aee857"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a23d0575e79fffc06dba35ebf43aee857"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_PTP_TX_SEND_SYNC_FRAME_MASK</b>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="separator:a23d0575e79fffc06dba35ebf43aee857"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab250fe374350b32cc023c3d3dd6cbd7a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ab250fe374350b32cc023c3d3dd6cbd7a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_PTP_TX_SEND_FOLLOWUP_FRAME_MASK</b>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="separator:ab250fe374350b32cc023c3d3dd6cbd7a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad8b49fecc058d895629fda0606f203a5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ad8b49fecc058d895629fda0606f203a5"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_PTP_TX_SEND_PDELAYREQ_FRAME_MASK</b>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="separator:ad8b49fecc058d895629fda0606f203a5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8bb6cfeae7bc98138b8fc4eaa6d852bc"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a8bb6cfeae7bc98138b8fc4eaa6d852bc"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_PTP_TX_SEND_PDELAYRESP_FRAME_MASK</b>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="separator:a8bb6cfeae7bc98138b8fc4eaa6d852bc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a23eea49756a97dddfbb3db3f0a8e07cc"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a23eea49756a97dddfbb3db3f0a8e07cc"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_PTP_TX_SEND_PDELAYRESPFOLLOWUP_FRAME_MASK</b>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="separator:a23eea49756a97dddfbb3db3f0a8e07cc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae267f03a2572c7e7f3ddc0690efd22f2"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ae267f03a2572c7e7f3ddc0690efd22f2"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_PTP_TX_SEND_ANNOUNCE_FRAME_MASK</b>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="separator:ae267f03a2572c7e7f3ddc0690efd22f2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afde2818bd966bb3c47caff8b87623527"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="afde2818bd966bb3c47caff8b87623527"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_PTP_TX_SEND_FRAME6_BIT_MASK</b>&#160;&#160;&#160;0x00000040</td></tr>
<tr class="separator:afde2818bd966bb3c47caff8b87623527"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa5e31639c5616bf524992995caac4fa6"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aa5e31639c5616bf524992995caac4fa6"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_PTP_TX_SEND_FRAME7_BIT_MASK</b>&#160;&#160;&#160;0x00000080</td></tr>
<tr class="separator:aa5e31639c5616bf524992995caac4fa6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a21ab07b9b48b97188fb2293aae38e338"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a21ab07b9b48b97188fb2293aae38e338"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_PTP_TX_WAIT_SYNC_FRAME_MASK</b>&#160;&#160;&#160;0x00000100</td></tr>
<tr class="separator:a21ab07b9b48b97188fb2293aae38e338"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a88498b811411a5382baea9ded3464014"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a88498b811411a5382baea9ded3464014"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_PTP_TX_WAIT_FOLLOWUP_FRAME_MASK</b>&#160;&#160;&#160;0x00000200</td></tr>
<tr class="separator:a88498b811411a5382baea9ded3464014"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5064c36e318853f7226c8438457d9ef6"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a5064c36e318853f7226c8438457d9ef6"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_PTP_TX_WAIT_PDELAYREQ_FRAME_MASK</b>&#160;&#160;&#160;0x00000400</td></tr>
<tr class="separator:a5064c36e318853f7226c8438457d9ef6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a324953095985f3ee1574fddccf0a91e8"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a324953095985f3ee1574fddccf0a91e8"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_PTP_TX_WAIT_PDELAYRESP_FRAME_MASK</b>&#160;&#160;&#160;0x00000800</td></tr>
<tr class="separator:a324953095985f3ee1574fddccf0a91e8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6fce6714f2e7b0cf27bc62a4496393ee"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a6fce6714f2e7b0cf27bc62a4496393ee"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_PTP_TX_WAIT_PDELAYRESPFOLLOWUP_FRAME_MASK</b>&#160;&#160;&#160;0x00001000</td></tr>
<tr class="separator:a6fce6714f2e7b0cf27bc62a4496393ee"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab9f4b67472363a3d8634fb8365604e41"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ab9f4b67472363a3d8634fb8365604e41"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_PTP_TX_WAIT_ANNOUNCE_FRAME_MASK</b>&#160;&#160;&#160;0x00002000</td></tr>
<tr class="separator:ab9f4b67472363a3d8634fb8365604e41"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a40c9512de41a4db77e7e40fb054449e1"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a40c9512de41a4db77e7e40fb054449e1"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_PTP_TX_WAIT_FRAME6_BIT_MASK</b>&#160;&#160;&#160;0x00004000</td></tr>
<tr class="separator:a40c9512de41a4db77e7e40fb054449e1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a18a2f61a3c12d8b2e91530301f0e6f09"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a18a2f61a3c12d8b2e91530301f0e6f09"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_PTP_TX_WAIT_FRAME7_BIT_MASK</b>&#160;&#160;&#160;0x00008000</td></tr>
<tr class="separator:a18a2f61a3c12d8b2e91530301f0e6f09"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a88ef3e83aa27122b0fbdfb29c995bfa1"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a88ef3e83aa27122b0fbdfb29c995bfa1"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_PTP_TX_WAIT_ALL_FRAMES_MASK</b>&#160;&#160;&#160;0x0000FF00</td></tr>
<tr class="separator:a88ef3e83aa27122b0fbdfb29c995bfa1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af5a5d6b95595b009cac927c93bce75db"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="af5a5d6b95595b009cac927c93bce75db"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_PTP_TX_PACKET_FIELD_MASK</b>&#160;&#160;&#160;0x00070000</td></tr>
<tr class="separator:af5a5d6b95595b009cac927c93bce75db"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">AVB Rx PTP Control Register</div></td></tr>
<tr class="memitem:a18d5b09853695aa9381fd95fed1f40e5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a18d5b09853695aa9381fd95fed1f40e5"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_PTP_RX_CLEAR_BIT_MASK</b>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="separator:a18d5b09853695aa9381fd95fed1f40e5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5ec2c4da8fb6fa9f3c6f45de94b91e0b"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a5ec2c4da8fb6fa9f3c6f45de94b91e0b"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_PTP_RX_PACKET_FIELD_MASK</b>&#160;&#160;&#160;0x00000F00</td></tr>
<tr class="separator:a5ec2c4da8fb6fa9f3c6f45de94b91e0b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">AVB Rx Filter Control Register</div></td></tr>
<tr class="memitem:ae94f247e58d65211d9053d7b4cb48b18"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ae94f247e58d65211d9053d7b4cb48b18"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_RX_AV_VLAN_PRIORITY_A_MASK</b>&#160;&#160;&#160;0x00000007</td></tr>
<tr class="separator:ae94f247e58d65211d9053d7b4cb48b18"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7af8ceaa6279a4d27142e9bd4d293d6f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a7af8ceaa6279a4d27142e9bd4d293d6f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_RX_AV_VLAN_VID_A_MASK</b>&#160;&#160;&#160;0x00007FF8</td></tr>
<tr class="separator:a7af8ceaa6279a4d27142e9bd4d293d6f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5d1c16c77f210dfd12bacf94781e4eed"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a5d1c16c77f210dfd12bacf94781e4eed"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_RX_AV_VLAN_MATCH_MODE_MASK</b>&#160;&#160;&#160;0x00008000</td></tr>
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<tr class="memitem:ac38842ef291cd5ceb584c48e464d33da"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ac38842ef291cd5ceb584c48e464d33da"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_RX_AV_VLAN_PRIORITY_B_MASK</b>&#160;&#160;&#160;0x00070000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_RX_AV_VLAN_VID_B_MASK</b>&#160;&#160;&#160;0x7FF80000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_RX_LEGACY_PROMISCUOUS_MODE_MASK</b>&#160;&#160;&#160;0x80000000</td></tr>
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<tr><td colspan="2"><div class="groupHeader">AVB Tx rate control sendSlope</div></td></tr>
<tr class="memitem:ad4b5a63b9b5b51ce819fa6ee77554991"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ad4b5a63b9b5b51ce819fa6ee77554991"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_TX_SENDSLOPE_MASK</b>&#160;&#160;&#160;0X000FFFFF</td></tr>
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<tr><td colspan="2"><div class="groupHeader">AVB Tx rate control idleSlope</div></td></tr>
<tr class="memitem:af5c9bc10a265a602afc3ce1bb30e86f1"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="af5c9bc10a265a602afc3ce1bb30e86f1"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_TX_IDLESLOPE_MASK</b>&#160;&#160;&#160;0X000FFFFF</td></tr>
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<tr><td colspan="2"><div class="groupHeader">AVB Tx rate control hiLimit</div></td></tr>
<tr class="memitem:a811447187119ec75d8db80e6e14fb022"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a811447187119ec75d8db80e6e14fb022"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_TX_HILIMIT_MASK</b>&#160;&#160;&#160;0X01FFFFFF</td></tr>
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<tr><td colspan="2"><div class="groupHeader">AVB Tx rate control loLimit</div></td></tr>
<tr class="memitem:a67e5406a645fc48ffb8556ae4a152ea3"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a67e5406a645fc48ffb8556ae4a152ea3"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_TX_LOLIMIT_MASK</b>&#160;&#160;&#160;0X01FFFFFF</td></tr>
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<tr><td colspan="2"><div class="groupHeader">RTC field Registers</div></td></tr>
<tr class="memitem:a9395b306d75d0cbc3302e3f278dad5f5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a9395b306d75d0cbc3302e3f278dad5f5"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_RTC_NS_MASK</b>&#160;&#160;&#160;0x3FFFFFFF</td></tr>
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<tr class="memitem:a9af5bf4ea5b56401b2f169c0dcd35312"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a9af5bf4ea5b56401b2f169c0dcd35312"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_RTC_SEC_LOWER_MASK</b>&#160;&#160;&#160;0xFFFFFFFF</td></tr>
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<tr class="memitem:a336c8d9bbe3a7fe0e799558a89b66a25"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a336c8d9bbe3a7fe0e799558a89b66a25"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_RTC_SEC_UPPER_MASK</b>&#160;&#160;&#160;0x0000FFFF</td></tr>
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<tr><td colspan="2"><div class="groupHeader">RTC Interrupt Clear Register</div></td></tr>
<tr class="memitem:abdd240f1c10b68d09feb9aade3d23643"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="abdd240f1c10b68d09feb9aade3d23643"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_RTC_INCREMENT_VALUE_MASK</b>&#160;&#160;&#160;0x03FFFFFF</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_RTC_INCREMENT_VALUE_MASK</b>&#160;&#160;&#160;0x03FFFFFF</td></tr>
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<tr class="memitem:a468abe5b9d120f730960225526755663"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a468abe5b9d120f730960225526755663"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_RTC_CLEAR_INT_MASK</b>&#160;&#160;&#160;0x00000000</td></tr>
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<tr><td colspan="2"><div class="groupHeader">RTC Increment Register</div></td></tr>
<tr class="memitem:aca5791394dd0b429d4c49559d0e1503c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xavb__hw_8h.html#aca5791394dd0b429d4c49559d0e1503c">XAVB_RTC_INCREMENT_NOMINAL_RATE</a>&#160;&#160;&#160;0x00800000</td></tr>
<tr class="memdesc:aca5791394dd0b429d4c49559d0e1503c"><td class="mdescLeft">&#160;</td><td class="mdescRight">This value assumes a 125MHz rtc_clock.  <a href="#aca5791394dd0b429d4c49559d0e1503c">More...</a><br/></td></tr>
<tr class="separator:aca5791394dd0b429d4c49559d0e1503c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a870c4aa143bd3d85e0b1c48e1871ccb9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xavb__hw_8h.html#a870c4aa143bd3d85e0b1c48e1871ccb9">XAVB_RTC_400PPM_OFFSET</a>&#160;&#160;&#160;0x00004189</td></tr>
<tr class="memdesc:a870c4aa143bd3d85e0b1c48e1871ccb9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Add some rails so that recovery is possible after a string of bad pDelay values.  <a href="#a870c4aa143bd3d85e0b1c48e1871ccb9">More...</a><br/></td></tr>
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<tr><td colspan="2"><div class="groupHeader">RTC 8k phase offset Register</div></td></tr>
<tr class="memitem:a4d12ac85a50cb0b96188e43b22207965"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a4d12ac85a50cb0b96188e43b22207965"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_RTC_8K_PHASE_OFFSET_MASK</b>&#160;&#160;&#160;0x3FFFFFFF</td></tr>
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<tr><td colspan="2"><div class="groupHeader">S/W Reset Register</div></td></tr>
<tr class="memitem:ad4c2b07c843637a61dab226fee606a17"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ad4c2b07c843637a61dab226fee606a17"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_SW_RESET_TX_AND_RX_PATHS</b>&#160;&#160;&#160;0x00000003</td></tr>
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<tr><td colspan="2"><div class="groupHeader">AVB MAC MDIO register address space.</div></td></tr>
<tr class="memitem:a3230e39c8fefe1c6ddc5b8019d0c0b48"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a3230e39c8fefe1c6ddc5b8019d0c0b48"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_MAC_MDIO_BASE_OFFSET</b>&#160;&#160;&#160;0x00006000</td></tr>
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<tr><td colspan="2"><div class="groupHeader">MDIO valid data mask (MDIO registers are all 16-bits).</div></td></tr>
<tr class="memitem:a94694ac1d352857d2fe6ff8b6e21d762"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a94694ac1d352857d2fe6ff8b6e21d762"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_MAC_MDIO_DATA_MASK</b>&#160;&#160;&#160;0x0000FFFF</td></tr>
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<tr><td colspan="2"><div class="groupHeader">MAC Statistic Counter names and CounterID.</div></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_STATS_BYTES_TRANSMITTED</b>&#160;&#160;&#160;0x00000000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_STATS_BYTES_RECEIVED</b>&#160;&#160;&#160;0x00000001</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_STATS_UNDERSIZED_FRAMES_RECEIVED</b>&#160;&#160;&#160;0x00000002</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_STATS_FRAGMENT_FRAMES_RECEIVED</b>&#160;&#160;&#160;0x00000003</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_STATS_64_BYTE_FRAMES_RECEIVED_OK</b>&#160;&#160;&#160;0x00000004</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_STATS_65_TO_127_BYTE_FRAMES_RECEIVED_OK</b>&#160;&#160;&#160;0x00000005</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_STATS_128_TO_255_BYTE_FRAMES_RECEIVED_OK</b>&#160;&#160;&#160;0x00000006</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_STATS_256_TO_511_BYTE_FRAMES_RECEIVED_OK</b>&#160;&#160;&#160;0x00000007</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_STATS_512_TO_1023_BYTE_FRAMES_RECEIVED_OK</b>&#160;&#160;&#160;0x00000008</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_STATS_1024_TO_1518_BYTE_FRAMES_RECEIVED_OK</b>&#160;&#160;&#160;0x00000009</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_STATS_OVERSIZED_FRAMES_RECEIVED_OK</b>&#160;&#160;&#160;0x0000000A</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_STATS_64_BYTE_FRAMES_TRANSMITTED_OK</b>&#160;&#160;&#160;0x0000000B</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_STATS_65_TO_127_BYTE_FRAMES_TRANSMITTED_OK</b>&#160;&#160;&#160;0x0000000C</td></tr>
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<tr class="memitem:a08ea1e465a3acdfd48c7ab7704d72db9"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a08ea1e465a3acdfd48c7ab7704d72db9"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_STATS_128_TO_255_BYTE_FRAMES_TRANSMITTED_OK</b>&#160;&#160;&#160;0x0000000D</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_STATS_256_TO_511_BYTE_FRAMES_TRANSMITTED_OK</b>&#160;&#160;&#160;0x0000000E</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_STATS_512_TO_1023_BYTE_FRAMES_TRANSMITTED_OK</b>&#160;&#160;&#160;0x0000000F</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_STATS_1024_TO_1518_BYTE_FRAMES_TRANSMITTED_OK</b>&#160;&#160;&#160;0x00000010</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_STATS_OVERSIZE_FRAMES_TRANSMITTED_OK</b>&#160;&#160;&#160;0x00000011</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_STATS_FRAMES_RECEIVED_OK</b>&#160;&#160;&#160;0x00000012</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_STATS_FCS_ERRORS</b>&#160;&#160;&#160;0x00000013</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_STATS_BROADCAST_FRAMES_RECEIVED_OK</b>&#160;&#160;&#160;0x00000014</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_STATS_MULTICAST_FRAMES_RECEIVED_OK</b>&#160;&#160;&#160;0x00000015</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_STATS_CONTROL_FRAMES_RECEIVED_OK</b>&#160;&#160;&#160;0x00000016</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_STATS_LENGTH_TYPE_OUT_OF_RANGE</b>&#160;&#160;&#160;0x00000017</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_STATS_VLAN_TAGGED_FRAMES_RECEIVED_OK</b>&#160;&#160;&#160;0x00000018</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_STATS_PAUSE_FRAMES_RECEIVED_OK</b>&#160;&#160;&#160;0x00000019</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_STATS_CONTROL_FRAMES_WITH_UNSUPPORTED_OPCODE</b>&#160;&#160;&#160;0x0000001A</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_STATS_FRAMES_TRANSMITTED</b>&#160;&#160;&#160;0x0000001B</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_STATS_BROADCAST_FRAMES_TRANSMITTED</b>&#160;&#160;&#160;0x0000001C</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_STATS_MULTICAST_FRAMES_TRANSMITTED</b>&#160;&#160;&#160;0x0000001D</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_STATS_UNDERRUN_ERRORS</b>&#160;&#160;&#160;0x0000001E</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_STATS_CONTROL_FRAMES_TRANSMITTED_OK</b>&#160;&#160;&#160;0x0000001F</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_STATS_VLAN_TAGGED_FRAMES_TRANSMITTED_OK</b>&#160;&#160;&#160;0x00000020</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_STATS_PAUSE_FRAMES_TRANSMITTED_OK</b>&#160;&#160;&#160;0x00000021</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_STATS_SINGLE_COLLISION_FRAMES</b>&#160;&#160;&#160;0x00000022</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_STATS_MULTI_COLLISION_FRAMES</b>&#160;&#160;&#160;0x00000023</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_STATS_DEFERRAL_FRAMES</b>&#160;&#160;&#160;0x00000024</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_STATS_LATE_COLLISION_FRAMES</b>&#160;&#160;&#160;0x00000025</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_STATS_EXCESS_COLLISION_FRAMES</b>&#160;&#160;&#160;0x00000026</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_STATS_EXCESS_DEFERRAL_FRAMES</b>&#160;&#160;&#160;0x00000027</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_STATS_CARRIER_SENSE_ERRORS</b>&#160;&#160;&#160;0x00000028</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAVB_STATS_ALIGNMENT_ERRORS</b>&#160;&#160;&#160;0x00000029</td></tr>
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</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:a18111ab5a605391b7a45186761ef671b"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xavb__hw_8h.html#a18111ab5a605391b7a45186761ef671b">XAvbMac_ReadStats</a> (u32 BaseAddress, u32 CounterId, <a class="el" href="struct_x_avb___uint64.html">XAvb_Uint64</a> *Value)</td></tr>
<tr class="memdesc:a18111ab5a605391b7a45186761ef671b"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function reads the given Ethernet Statistic Register.  <a href="#a18111ab5a605391b7a45186761ef671b">More...</a><br/></td></tr>
<tr class="separator:a18111ab5a605391b7a45186761ef671b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adbb46fbeb6b3bb40e8067ea6f8a0776c"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xavb__hw_8h.html#adbb46fbeb6b3bb40e8067ea6f8a0776c">XAvb_ReadRtc</a> (u32 BaseAddress, <a class="el" href="struct_x_avb___rtc_format.html">XAvb_RtcFormat</a> *RtcValue)</td></tr>
<tr class="memdesc:adbb46fbeb6b3bb40e8067ea6f8a0776c"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function reads the current Real Time Counter (RTC) value.  <a href="#adbb46fbeb6b3bb40e8067ea6f8a0776c">More...</a><br/></td></tr>
<tr class="separator:adbb46fbeb6b3bb40e8067ea6f8a0776c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a07f6e740f5623df870beea331507baf3"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xavb__hw_8h.html#a07f6e740f5623df870beea331507baf3">XAvb_WriteRtcOffset</a> (u32 BaseAddress, <a class="el" href="struct_x_avb___rtc_format.html">XAvb_RtcFormat</a> *RtcValue)</td></tr>
<tr class="memdesc:a07f6e740f5623df870beea331507baf3"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function writes to the Real Time Counter (RTC) Offset Registers.  <a href="#a07f6e740f5623df870beea331507baf3">More...</a><br/></td></tr>
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<h2 class="groupheader">Macro Definition Documentation</h2>
<a class="anchor" id="ae5d89c2164737985208dda027b8d0387"></a>
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          <td class="memname">#define XAVB_MAC_FC_REG_OFFSET&#160;&#160;&#160;0x0000040c</td>
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<p>MAC Flow Control Register. </p>

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          <td class="memname">#define XAVB_MAC_RX_REG0_OFFSET&#160;&#160;&#160;0x00000400</td>
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<p>MAC Rx Config Register 0. </p>

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          <td class="memname">#define XAVB_MAC_RX_REG1_OFFSET&#160;&#160;&#160;0x00000404</td>
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<p>MAC Rx Config Register 1. </p>

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</div>
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          <td class="memname">#define XAVB_MAC_SPD_REG_OFFSET&#160;&#160;&#160;0x00000410</td>
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<p>MAC Speed Control Register. </p>

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          <td class="memname">#define XAVB_MAC_TX_REG_OFFSET&#160;&#160;&#160;0x00000408</td>
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<p>MAC Tx Config Register. </p>

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          <td class="memname">#define XAVB_PTP_RX_CONTROL_OFFSET&#160;&#160;&#160;0x00012004</td>
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<p>Rx PTP Control Reg. </p>

<p>Referenced by <a class="el" href="xavb_8h.html#a99019d3795040dd7110d47aaa598ab7b">XAvb_PtpRxInterruptHandler()</a>.</p>

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          <td class="memname">#define XAVB_PTP_TX_CONTROL_OFFSET&#160;&#160;&#160;0x00012000</td>
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</div><div class="memdoc">

<p>Tx PTP Control Reg. </p>

<p>Referenced by <a class="el" href="xavb__ptp__packets_8c.html#aeeaf9984303a07b8935d4a391f0ca188">XAvb_MasterSendAnnounce()</a>, <a class="el" href="xavb__ptp__packets_8c.html#a989d44c98695fd6f286858f8b7976e3f">XAvb_MasterSendFollowUp()</a>, <a class="el" href="xavb__ptp__packets_8c.html#ae239544f086bc86572b8e2d7e408a028">XAvb_MasterSendSync()</a>, <a class="el" href="xavb__ptp__packets_8c.html#a2e3f462007beb73497bbded566d7f364">XAvb_SendPDelayReq()</a>, <a class="el" href="xavb__ptp__packets_8c.html#a63281acd385453959b333154bca2d9c7">XAvb_SendPDelayResp()</a>, <a class="el" href="xavb__ptp__packets_8c.html#a2c1081cde03d0c53bc508927111fe87c">XAvb_SendPDelayRespFollowUp()</a>, and <a class="el" href="xavb__ptp__packets_8c.html#afcb3695de30c54e17e3c3e0a461ab0eb">XAvb_WaitOnTxPtpQueue()</a>.</p>

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          <td class="memname">#define XAvb_ReadPtpBuffer</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">PtpPacketBaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">PtpPacketOffset&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;Xil_In32(BaseAddress + PtpPacketBaseAddress + PtpPacketOffset)</td>
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<p>This macro reads from the given PTP frame buffer. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the device </td></tr>
    <tr><td class="paramname">PtpPacketBaseAddress</td><td>is the base address of the frame in the PTP BRAM packet buffer </td></tr>
    <tr><td class="paramname">PtpPacketOffset</td><td>is the offset address within the PTP frame</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The 32-bit value of the register</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>Referenced by <a class="el" href="xavb_8h.html#a5ee8dd26b932ff82daa0dc87fd6d38d8">XAvb_CalcRtcOffset()</a>, <a class="el" href="xavb_8h.html#a3ce07f766a1033fab5a1981e947db52e">XAvb_CaptureNanoSec()</a>, <a class="el" href="xavb__ptp__packets_8c.html#afb8650c4c94082dc746db9ec0259e1cb">XAvb_DecodeRxFollowUp()</a>, <a class="el" href="xavb__ptp__packets_8c.html#acc5beb09f67f655b7eb8eb51b3cd2d8a">XAvb_DecodeRxPDelayResp()</a>, <a class="el" href="xavb__ptp__packets_8c.html#afd53beaf90143fc360dc6276ba1c49f9">XAvb_DecodeRxPDelayRespFollowUp()</a>, <a class="el" href="xavb__ptp__packets_8c.html#ab9afff73e01faafdc8ce9f8e0ee8d4de">XAvb_DecodeRxSignaling()</a>, <a class="el" href="xavb__ptp__packets_8c.html#a3ed6d94f92c94a88dce9444e8a27fe8a">XAvb_DecodeRxSync()</a>, <a class="el" href="xavb__ptp__packets_8c.html#a2f2030902e6748712f30a59a62dff010">XAvb_GetPortIdentity()</a>, <a class="el" href="xavb__ptp__packets_8c.html#a99e7a11b4a2960e116891ba88bbb6c84">XAvb_IncSequenceId()</a>, <a class="el" href="xavb__ptp__packets_8c.html#aaefe66ad0ca9e6af05129765cca4c3df">XAvb_IsRxFramePTP()</a>, <a class="el" href="xavb__ptp__packets_8c.html#a989d44c98695fd6f286858f8b7976e3f">XAvb_MasterSendFollowUp()</a>, <a class="el" href="xavb__ptp__packets_8c.html#ae239544f086bc86572b8e2d7e408a028">XAvb_MasterSendSync()</a>, <a class="el" href="xavb_8h.html#a99019d3795040dd7110d47aaa598ab7b">XAvb_PtpRxInterruptHandler()</a>, <a class="el" href="xavb__ptp__bmca_8c.html#a7c77fd7953811584a36001e5e74165b3">XAvb_ReadAnnounceFrame()</a>, <a class="el" href="xavb__ptp__bmca_8c.html#aa66e9752ef47bf7eafe4784cb59e1093">XAvb_ReadAnnounceReceiptTimeout()</a>, <a class="el" href="xavb__ptp__packets_8c.html#a2e3f462007beb73497bbded566d7f364">XAvb_SendPDelayReq()</a>, <a class="el" href="xavb__ptp__packets_8c.html#a63281acd385453959b333154bca2d9c7">XAvb_SendPDelayResp()</a>, <a class="el" href="xavb__ptp__packets_8c.html#a2c1081cde03d0c53bc508927111fe87c">XAvb_SendPDelayRespFollowUp()</a>, <a class="el" href="xavb__ptp__packets_8c.html#a42cd78e966447edcb45a0f419cc84cb8">XAvb_SetupSourcePortIdentity()</a>, <a class="el" href="xavb__ptp__packets_8c.html#a9c3933020b616a2a57b6229bce6f6151">XAvb_UpdateLogMeanMessageInterval()</a>, and <a class="el" href="xavb__ptp__packets_8c.html#ae73f986654f8315075dd1c3158087605">XAvb_WriteToMultipleTxPtpFrames()</a>.</p>

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          <td class="memname">#define XAvb_ReadReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;Xil_In32((BaseAddress) + (RegOffset))</td>
        </tr>
      </table>
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<p>This macro reads from the given AVB core register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the device </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the register offset to be read</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The 32-bit value of the register</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>Referenced by <a class="el" href="xavb_8h.html#a2a46d84127016dacb2823b953acbfd20">XAvb_Adjust8kClock()</a>, <a class="el" href="xavb_8h.html#a5ee8dd26b932ff82daa0dc87fd6d38d8">XAvb_CalcRtcOffset()</a>, <a class="el" href="xavb__ptp__packets_8c.html#aeeaf9984303a07b8935d4a391f0ca188">XAvb_MasterSendAnnounce()</a>, <a class="el" href="xavb__ptp__packets_8c.html#a989d44c98695fd6f286858f8b7976e3f">XAvb_MasterSendFollowUp()</a>, <a class="el" href="xavb__ptp__packets_8c.html#ae239544f086bc86572b8e2d7e408a028">XAvb_MasterSendSync()</a>, <a class="el" href="xavb_8h.html#a99019d3795040dd7110d47aaa598ab7b">XAvb_PtpRxInterruptHandler()</a>, <a class="el" href="xavb__ptp__packets_8c.html#a63281acd385453959b333154bca2d9c7">XAvb_SendPDelayResp()</a>, <a class="el" href="xavb_8h.html#a888d220aeb387018ce33558e08d0166e">XAvb_SetupRxFilterControlMatchMode()</a>, <a class="el" href="xavb_8h.html#a4a970ecc2621c88825ecc3f01ff1c4ad">XAvb_SetupRxFilterControlPcp()</a>, <a class="el" href="xavb_8h.html#afb10d8fd68257130d0fc50bfe71ad3e6">XAvb_SetupRxFilterControlVid()</a>, <a class="el" href="xavb_8h.html#ada9dd75eb576b0e600686514fbea45e3">XAvb_UpdateRtcIncrement()</a>, and <a class="el" href="xavb__ptp__packets_8c.html#afcb3695de30c54e17e3c3e0a461ab0eb">XAvb_WaitOnTxPtpQueue()</a>.</p>

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<a class="anchor" id="a870c4aa143bd3d85e0b1c48e1871ccb9"></a>
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          <td class="memname">#define XAVB_RTC_400PPM_OFFSET&#160;&#160;&#160;0x00004189</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Add some rails so that recovery is possible after a string of bad pDelay values. </p>
<p>The RTC should be able to lock to within 100ppm of the slowest allowable clock (25 MHz). This equates to +/-4ps. Let's arbitrarily set the rails to 400ppm (+/-16ps) just in case someone decides to use a particularly bad oscillator. The lowest 20 bits of NewIncrement are fractions of a nanosecond, which equates to +/- 0x04189 </p>

<p>Referenced by <a class="el" href="xavb_8h.html#ada9dd75eb576b0e600686514fbea45e3">XAvb_UpdateRtcIncrement()</a>.</p>

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<a class="anchor" id="af86466362cc51296ae22fd1cb6c1d6ad"></a>
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        <tr>
          <td class="memname">#define XAVB_RTC_8K_OFFSET_OFFSET&#160;&#160;&#160;0x00012824</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>RTC 8k phase offset. </p>

<p>Referenced by <a class="el" href="xavb_8h.html#a2a46d84127016dacb2823b953acbfd20">XAvb_Adjust8kClock()</a>.</p>

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<a class="anchor" id="a2f724f6845f2fc8b62dc841ef36525d5"></a>
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<div class="memproto">
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        <tr>
          <td class="memname">#define XAVB_RTC_CLEAR_INT_OFFSET&#160;&#160;&#160;0x00012820</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>RTC Interrupt Clear. </p>

<p>Referenced by <a class="el" href="xavb_8h.html#aab96c1602bda46380e25d0bb03a8ac01">XAvb_PtpTimerInterruptHandler()</a>.</p>

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        <tr>
          <td class="memname">#define XAVB_RTC_INCREMENT_NOMINAL_RATE&#160;&#160;&#160;0x00800000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This value assumes a 125MHz rtc_clock. </p>

<p>Referenced by <a class="el" href="xavb__ptp__bmca_8c.html#a5ef1c55c51f5781c4395ff20cc07f410">XAvb_BecomeRtcMaster()</a>, and <a class="el" href="xavb_8h.html#ada9dd75eb576b0e600686514fbea45e3">XAvb_UpdateRtcIncrement()</a>.</p>

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<a class="anchor" id="a48d76d16f8d685a65a1216614e548071"></a>
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<div class="memproto">
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        <tr>
          <td class="memname">#define XAVB_RTC_INCREMENT_OFFSET&#160;&#160;&#160;0x00012810</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>RTC Increment Reg. </p>

<p>Referenced by <a class="el" href="xavb__ptp__bmca_8c.html#a5ef1c55c51f5781c4395ff20cc07f410">XAvb_BecomeRtcMaster()</a>, and <a class="el" href="xavb_8h.html#ada9dd75eb576b0e600686514fbea45e3">XAvb_UpdateRtcIncrement()</a>.</p>

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<a class="anchor" id="a17b4489a857a0fcb761a529b749d5ad3"></a>
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<div class="memproto">
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        <tr>
          <td class="memname">#define XAVB_RTC_NANOSEC_OFFSET&#160;&#160;&#160;0x00012800</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>RTC ns offset Reg. </p>

<p>Referenced by <a class="el" href="xavb_8h.html#a2a46d84127016dacb2823b953acbfd20">XAvb_Adjust8kClock()</a>, <a class="el" href="xavb_8h.html#a5ee8dd26b932ff82daa0dc87fd6d38d8">XAvb_CalcRtcOffset()</a>, <a class="el" href="xavb__ptp__packets_8c.html#a989d44c98695fd6f286858f8b7976e3f">XAvb_MasterSendFollowUp()</a>, <a class="el" href="xavb__ptp__packets_8c.html#a63281acd385453959b333154bca2d9c7">XAvb_SendPDelayResp()</a>, and <a class="el" href="xavb__hw_8h.html#a07f6e740f5623df870beea331507baf3">XAvb_WriteRtcOffset()</a>.</p>

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<a class="anchor" id="a59f550eaa57148613974c4aa5628bfb4"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XAVB_RTC_NANOSEC_VALUE_OFFSET&#160;&#160;&#160;0x00012814</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>RTC ns value Reg. </p>

<p>Referenced by <a class="el" href="xavb__ptp__packets_8c.html#aeeaf9984303a07b8935d4a391f0ca188">XAvb_MasterSendAnnounce()</a>, <a class="el" href="xavb__ptp__packets_8c.html#ae239544f086bc86572b8e2d7e408a028">XAvb_MasterSendSync()</a>, <a class="el" href="xavb__hw_8h.html#adbb46fbeb6b3bb40e8067ea6f8a0776c">XAvb_ReadRtc()</a>, and <a class="el" href="xavb__ptp__packets_8c.html#a63281acd385453959b333154bca2d9c7">XAvb_SendPDelayResp()</a>.</p>

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<a class="anchor" id="acc7285ad5177c30185fcd6e39992865b"></a>
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<div class="memproto">
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          <td class="memname">#define XAVB_RTC_SEC_LOWER_OFFSET&#160;&#160;&#160;0x00012808</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>RTC sec[31:0] offset. </p>

<p>Referenced by <a class="el" href="xavb__hw_8h.html#a07f6e740f5623df870beea331507baf3">XAvb_WriteRtcOffset()</a>.</p>

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<a class="anchor" id="aa71292011b875c192d09141638c3a4e1"></a>
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<div class="memproto">
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        <tr>
          <td class="memname">#define XAVB_RTC_SEC_LOWER_VALUE_OFFSET&#160;&#160;&#160;0x00012818</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>RTC sec[31:0] value. </p>

<p>Referenced by <a class="el" href="xavb_8h.html#a5ee8dd26b932ff82daa0dc87fd6d38d8">XAvb_CalcRtcOffset()</a>, <a class="el" href="xavb__ptp__packets_8c.html#aeeaf9984303a07b8935d4a391f0ca188">XAvb_MasterSendAnnounce()</a>, <a class="el" href="xavb__ptp__packets_8c.html#ae239544f086bc86572b8e2d7e408a028">XAvb_MasterSendSync()</a>, <a class="el" href="xavb__hw_8h.html#adbb46fbeb6b3bb40e8067ea6f8a0776c">XAvb_ReadRtc()</a>, and <a class="el" href="xavb__ptp__packets_8c.html#a63281acd385453959b333154bca2d9c7">XAvb_SendPDelayResp()</a>.</p>

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<a class="anchor" id="ac8683f10accad0c3fbb9ed86f7e63577"></a>
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<div class="memproto">
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        <tr>
          <td class="memname">#define XAVB_RTC_SEC_UPPER_OFFSET&#160;&#160;&#160;0x0001280C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>RTC sec[47:32] offset. </p>

<p>Referenced by <a class="el" href="xavb__hw_8h.html#a07f6e740f5623df870beea331507baf3">XAvb_WriteRtcOffset()</a>.</p>

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<div class="memproto">
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          <td class="memname">#define XAVB_RTC_SEC_UPPER_VALUE_OFFSET&#160;&#160;&#160;0x0001281C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>RTC sec[47:32] value. </p>

<p>Referenced by <a class="el" href="xavb__ptp__packets_8c.html#ae239544f086bc86572b8e2d7e408a028">XAvb_MasterSendSync()</a>, <a class="el" href="xavb__hw_8h.html#adbb46fbeb6b3bb40e8067ea6f8a0776c">XAvb_ReadRtc()</a>, and <a class="el" href="xavb__ptp__packets_8c.html#a63281acd385453959b333154bca2d9c7">XAvb_SendPDelayResp()</a>.</p>

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<a class="anchor" id="aeb18774c7074b8558f6f3d92ee894308"></a>
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          <td class="memname">#define XAVB_RX_FILTER_CONTROL&#160;&#160;&#160;0x00012008</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Rx Filter Control Reg. </p>

<p>Referenced by <a class="el" href="xavb_8h.html#a888d220aeb387018ce33558e08d0166e">XAvb_SetupRxFilterControlMatchMode()</a>, <a class="el" href="xavb_8h.html#a4a970ecc2621c88825ecc3f01ff1c4ad">XAvb_SetupRxFilterControlPcp()</a>, and <a class="el" href="xavb_8h.html#afb10d8fd68257130d0fc50bfe71ad3e6">XAvb_SetupRxFilterControlVid()</a>.</p>

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<a class="anchor" id="ae9e3a0562e191d4ea8eb166f5deadef3"></a>
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          <td class="memname">#define XAVB_SW_RESET_OFFSET&#160;&#160;&#160;0x00012828</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>S/W Reset Reg. </p>

<p>Referenced by <a class="el" href="xavb_8h.html#af24c248c31c6c45cdb8a46f82de175c5">XAvb_Reset()</a>.</p>

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<a class="anchor" id="aa8ecc322bb424bdd59e02a09b7a91279"></a>
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          <td class="memname">#define XAVB_TX_HILIMIT&#160;&#160;&#160;0x00012014</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Tx rate hiLimit Reg. </p>

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<a class="anchor" id="a355862c65f81390538cf5e8b19493ea5"></a>
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          <td class="memname">#define XAVB_TX_IDLESLOPE&#160;&#160;&#160;0x00012010</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Tx rate idleSlope Reg. </p>

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<a class="anchor" id="a77bc297f703b667990fe302c8d7765ac"></a>
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          <td class="memname">#define XAVB_TX_LOLIMIT&#160;&#160;&#160;0x00012018</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Tx rate loLimit Reg. </p>

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<a class="anchor" id="a634b68c6d85a3fbadd2b6feb56a62d62"></a>
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<div class="memproto">
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          <td class="memname">#define XAVB_TX_SENDSLOPE&#160;&#160;&#160;0x0001200C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Tx rate sendSlope Reg. </p>

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          <td class="memname">#define XAvb_WritePtpBuffer</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">PtpPacketBaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">PtpPacketOffset, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Data&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;Xil_Out32(BaseAddress + PtpPacketBaseAddress + PtpPacketOffset, (Data))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This macro writes to the given PTP frame buffer. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the device </td></tr>
    <tr><td class="paramname">PtpPacketBaseAddress</td><td>is the base address of the frame in the PTP packet buffer </td></tr>
    <tr><td class="paramname">PtpPacketOffset</td><td>is the offset address within the PTP frame </td></tr>
    <tr><td class="paramname">Data</td><td>is the 32-bit value to write to the register</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>Referenced by <a class="el" href="xavb__ptp__packets_8c.html#a99e7a11b4a2960e116891ba88bbb6c84">XAvb_IncSequenceId()</a>, <a class="el" href="xavb__ptp__packets_8c.html#a989d44c98695fd6f286858f8b7976e3f">XAvb_MasterSendFollowUp()</a>, <a class="el" href="xavb__ptp__packets_8c.html#ae239544f086bc86572b8e2d7e408a028">XAvb_MasterSendSync()</a>, <a class="el" href="xavb__ptp__packets_8c.html#a63281acd385453959b333154bca2d9c7">XAvb_SendPDelayResp()</a>, <a class="el" href="xavb__ptp__packets_8c.html#a2c1081cde03d0c53bc508927111fe87c">XAvb_SendPDelayRespFollowUp()</a>, <a class="el" href="xavb__ptp__packets_8c.html#a42cd78e966447edcb45a0f419cc84cb8">XAvb_SetupSourcePortIdentity()</a>, <a class="el" href="xavb__ptp__packets_8c.html#a9c3933020b616a2a57b6229bce6f6151">XAvb_UpdateLogMeanMessageInterval()</a>, and <a class="el" href="xavb__ptp__packets_8c.html#ae73f986654f8315075dd1c3158087605">XAvb_WriteToMultipleTxPtpFrames()</a>.</p>

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<a class="anchor" id="a74f3dcc0fed12b1ee97541a109b8d98c"></a>
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<div class="memproto">
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          <td class="memname">#define XAvb_WriteReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Data&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;Xil_Out32((BaseAddress) + (RegOffset), (Data))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This macro writes to the given AVB core register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the device </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the register offset to be written </td></tr>
    <tr><td class="paramname">Data</td><td>is the 32-bit value to write to the register</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>Referenced by <a class="el" href="xavb_8h.html#a2a46d84127016dacb2823b953acbfd20">XAvb_Adjust8kClock()</a>, <a class="el" href="xavb__ptp__bmca_8c.html#a5ef1c55c51f5781c4395ff20cc07f410">XAvb_BecomeRtcMaster()</a>, <a class="el" href="xavb__ptp__packets_8c.html#aeeaf9984303a07b8935d4a391f0ca188">XAvb_MasterSendAnnounce()</a>, <a class="el" href="xavb__ptp__packets_8c.html#a989d44c98695fd6f286858f8b7976e3f">XAvb_MasterSendFollowUp()</a>, <a class="el" href="xavb__ptp__packets_8c.html#ae239544f086bc86572b8e2d7e408a028">XAvb_MasterSendSync()</a>, <a class="el" href="xavb_8h.html#aab96c1602bda46380e25d0bb03a8ac01">XAvb_PtpTimerInterruptHandler()</a>, <a class="el" href="xavb_8h.html#af24c248c31c6c45cdb8a46f82de175c5">XAvb_Reset()</a>, <a class="el" href="xavb__ptp__packets_8c.html#a2e3f462007beb73497bbded566d7f364">XAvb_SendPDelayReq()</a>, <a class="el" href="xavb__ptp__packets_8c.html#a63281acd385453959b333154bca2d9c7">XAvb_SendPDelayResp()</a>, <a class="el" href="xavb__ptp__packets_8c.html#a2c1081cde03d0c53bc508927111fe87c">XAvb_SendPDelayRespFollowUp()</a>, <a class="el" href="xavb_8h.html#a888d220aeb387018ce33558e08d0166e">XAvb_SetupRxFilterControlMatchMode()</a>, <a class="el" href="xavb_8h.html#a4a970ecc2621c88825ecc3f01ff1c4ad">XAvb_SetupRxFilterControlPcp()</a>, <a class="el" href="xavb_8h.html#afb10d8fd68257130d0fc50bfe71ad3e6">XAvb_SetupRxFilterControlVid()</a>, and <a class="el" href="xavb_8h.html#ada9dd75eb576b0e600686514fbea45e3">XAvb_UpdateRtcIncrement()</a>.</p>

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<a class="anchor" id="ac935987ce15937b9a2b77a104f559bde"></a>
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<div class="memproto">
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          <td class="memname">#define XAvbMac_ReadConfig</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;Xil_In32((BaseAddress) + (RegOffset))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This macro reads from the given TEMAC Configuration Register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the device </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the register offset to be read</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The 32-bit value of the register</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

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<a class="anchor" id="ae599ca8c254011bb4ee0191e32327ee9"></a>
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          <td class="memname">#define XAvbMac_ReadMdio</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Phyad, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Regad&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
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<b>Value:</b><div class="fragment"><div class="line">Xil_In32((BaseAddress) + XAVB_MAC_MDIO_BASE_OFFSET         \</div>
<div class="line">                                  + (((Phyad) &amp; 0x1F) &lt;&lt; 8)  \</div>
<div class="line">                                  + (((Regad) &amp; 0x1F) &lt;&lt; 3))</div>
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<p>This macro reads from the given MDIO Register using the TEMAC. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the device </td></tr>
    <tr><td class="paramname">Phyad</td><td>is the Physical Address of the PHY </td></tr>
    <tr><td class="paramname">Regad</td><td>is the Address of the MDIO register within the addressed PHY</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The 32-bit value of the register (upper 16-bits will be all 0's)</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

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          <td class="memname">#define XAvbMac_WriteConfig</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Data&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;Xil_Out32((BaseAddress) + (RegOffset), (Data))</td>
        </tr>
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<p>This macro writes to the given TEMAC Configuration Register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the device </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the register offset to be written </td></tr>
    <tr><td class="paramname">Data</td><td>is the 32-bit value to write to the register</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

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          <td class="memname">#define XAvbMac_WriteMdio</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Phyad, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Regad, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Data&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<b>Value:</b><div class="fragment"><div class="line">Xil_Out32(BaseAddress + XAVB_MAC_MDIO_BASE_OFFSET \</div>
<div class="line">                        + (((Phyad) &amp; 0x1F) &lt;&lt; 8)   \</div>
<div class="line">                        + (((Regad) &amp; 0x1F) &lt;&lt; 3),  \</div>
<div class="line">           (Data &amp; XAVB_MAC_MDIO_DATA_MASK))</div>
</div><!-- fragment -->
<p>This macro writes to the given MDIO Register using the TEMAC. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the device </td></tr>
    <tr><td class="paramname">Phyad</td><td>is the Physical Address of the PHY </td></tr>
    <tr><td class="paramname">Regad</td><td>is the Address of the MDIO register within the addressed PHY </td></tr>
    <tr><td class="paramname">Data</td><td>is the 32-bit value to write</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

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<h2 class="groupheader">Function Documentation</h2>
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          <td class="memname">void XAvb_ReadRtc </td>
          <td>(</td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>BaseAddress</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="struct_x_avb___rtc_format.html">XAvb_RtcFormat</a> *&#160;</td>
          <td class="paramname"><em>RtcValue</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function reads the current Real Time Counter (RTC) value. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the device </td></tr>
    <tr><td class="paramname">RtcValue</td><td>is a pointer to a struct in which to store the value read from the RTC (The RTC 48-bit seconds field and the 32-bit ns field of this struct are updated).</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This is provided as a basic function since the ns field MUST be read before the seconds/epoch registers (reading the ns samples the entire RTC in hardware). </dd></dl>

<p>References <a class="el" href="struct_x_avb___rtc_format.html#ad30a5df1748ad71907d830893f23cbba">XAvb_RtcFormat::NanoSeconds</a>, <a class="el" href="struct_x_avb___rtc_format.html#a5015cb1ee0a5eb14ef15e03225450a81">XAvb_RtcFormat::SecondsLower</a>, <a class="el" href="struct_x_avb___rtc_format.html#a84452962f60d5528bbb9da1df3c1bf7d">XAvb_RtcFormat::SecondsUpper</a>, <a class="el" href="xavb__hw_8h.html#a59f550eaa57148613974c4aa5628bfb4">XAVB_RTC_NANOSEC_VALUE_OFFSET</a>, <a class="el" href="xavb__hw_8h.html#aa71292011b875c192d09141638c3a4e1">XAVB_RTC_SEC_LOWER_VALUE_OFFSET</a>, and <a class="el" href="xavb__hw_8h.html#ae38e8307c8da64ba9f42516168855a8f">XAVB_RTC_SEC_UPPER_VALUE_OFFSET</a>.</p>

<p>Referenced by <a class="el" href="xavb_8h.html#a5ee8dd26b932ff82daa0dc87fd6d38d8">XAvb_CalcRtcOffset()</a>, and <a class="el" href="xavb__ptp__packets_8c.html#a2c1081cde03d0c53bc508927111fe87c">XAvb_SendPDelayRespFollowUp()</a>.</p>

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          <td class="memname">void XAvb_WriteRtcOffset </td>
          <td>(</td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>BaseAddress</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="struct_x_avb___rtc_format.html">XAvb_RtcFormat</a> *&#160;</td>
          <td class="paramname"><em>RtcValue</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function writes to the Real Time Counter (RTC) Offset Registers. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the device </td></tr>
    <tr><td class="paramname">RtcValue</td><td>is the nanoseconds and seconds offset values that should be written to the RTC.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This is provided as a basic function since the ns field MUST be written after the seconds/epoch offset registers (writing to the ns offset registers samples the entire RTC offset in hardware). </dd></dl>

<p>References <a class="el" href="struct_x_avb___rtc_format.html#ad30a5df1748ad71907d830893f23cbba">XAvb_RtcFormat::NanoSeconds</a>, <a class="el" href="struct_x_avb___rtc_format.html#a5015cb1ee0a5eb14ef15e03225450a81">XAvb_RtcFormat::SecondsLower</a>, <a class="el" href="struct_x_avb___rtc_format.html#a84452962f60d5528bbb9da1df3c1bf7d">XAvb_RtcFormat::SecondsUpper</a>, <a class="el" href="xavb__hw_8h.html#a17b4489a857a0fcb761a529b749d5ad3">XAVB_RTC_NANOSEC_OFFSET</a>, <a class="el" href="xavb__hw_8h.html#acc7285ad5177c30185fcd6e39992865b">XAVB_RTC_SEC_LOWER_OFFSET</a>, and <a class="el" href="xavb__hw_8h.html#ac8683f10accad0c3fbb9ed86f7e63577">XAVB_RTC_SEC_UPPER_OFFSET</a>.</p>

<p>Referenced by <a class="el" href="xavb_8h.html#a5ee8dd26b932ff82daa0dc87fd6d38d8">XAvb_CalcRtcOffset()</a>.</p>

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          <td class="memname">void XAvbMac_ReadStats </td>
          <td>(</td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>BaseAddress</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>CounterId</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="struct_x_avb___uint64.html">XAvb_Uint64</a> *&#160;</td>
          <td class="paramname"><em>Value</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function reads the given Ethernet Statistic Register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the device </td></tr>
    <tr><td class="paramname">CounterID</td><td>is the Statistic Counter to be read </td></tr>
    <tr><td class="paramname">Value</td><td>a pointer to the read value of the 64-bit value of the counter and it is updated by this function</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>The CounterID's defined here are the same as the Statistic Counter Addresses as used with the TEMAC core. Since each counter is 8-bytes wide, we must multiply these Counter ID's by 8 (or a left shift of 3) when mapping this into the PLB memory map. The 64-bit counter value is read as two separate 32-bit accesses. </dd></dl>

<p>References <a class="el" href="struct_x_avb___uint64.html#ab7c91a4902ebdcbdc5341def2e98bda2">XAvb_Uint64::Lower</a>, and <a class="el" href="struct_x_avb___uint64.html#a106cfc71a57bb8e01817eb6a20ed5347">XAvb_Uint64::Upper</a>.</p>

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